A Sub-pJ/Bit, Low-ER Mach-Zehnder-Based Transmitter for Chip-to-Chip Optical Interconnects

Designing high-speed and low-power interconnects is a challenge for high performance computing applications, while silicon photonics can provide attractive solutions to perform highdensity communications. This paper presents an electro-optic transmitter operating at 20 Gbps (gigabit per second), as a first step toward the demonstration of chip-to-chip optical links. The architecture is based on a dual-drive Mach-Zehnder interferometer co-integrated with a 55-nm CMOS driver. Design optimizations and trade-offs analysis enable low-energy and negligible bit error rate (BER