A 50-kW Air-Cooled SiC Inverter With 3-D Printing Enabled Power Module Packaging Structure and Genetic Algorithm Optimized Heatsinks

This article presents a systematic power stage design approach for a high-power density air-cooled inverter, which involves the utilization of emerging 1.7 kV silicon carbide (SiC) mosfet bare die engineering samples, heatsinks optimized with genetic algorithm, and built using three-dimensional prin...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE transactions on industry applications 2019-11, Vol.55 (6), p.6256-6265
Hauptverfasser: Wang, Zhiqiang, Chinthavali, Madhu, Campbell, Steven L., Wu, Tong, Ozpineci, Burak
Format: Artikel
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:This article presents a systematic power stage design approach for a high-power density air-cooled inverter, which involves the utilization of emerging 1.7 kV silicon carbide (SiC) mosfet bare die engineering samples, heatsinks optimized with genetic algorithm, and built using three-dimensional printing technology and integrated power modules with a novel packaging structure. The developed air-cooled inverter assembly is mainly composed of the SiC mosfet phase leg modules with split high-side and low-side switch submodules, which are attached to two separate heatsinks for increased heat dissipation area and reduced thermal resistance. The heatsink is designed using a co-simulation environment with finite element analysis in COMSOL and genetic algorithm in MATLAB. The primary design procedure, including bare die device characterization, loss calculation, thermal evaluation, and power module development, is elaborated. The proposed design approach is verified and validated through experiments at each stage of development. The experimental results show that the inverter California Energy Commission efficiency is 98.4%, and a power density of 75 W/in 3 is achieved with a sufficient junction temperature margin for semiconductor long-term reliability.
ISSN:0093-9994
1939-9367
DOI:10.1109/TIA.2019.2938471