A reconfigurable pipelined IDCT for low-energy video processing

In video processing, average data rates are often significantly lower than a given maximum possible rate. Consequently, VLSI systems that are capable of processing video streams at the maximum data rates specified in video standards can be excessively dissipative at low data rates. Such inefficiencies are particularly pronounced in heavily pipelined designs, in which registers account for the bulk of the energy dissipation. This paper describes a novel methodology for designing reconfigurable pipelined datapaths that achieve very low energy dissipation by adapting their structures to their computational requirements. In our reconfigurable datapaths, energy is saved by disabling and bypassing an appropriate number of dissipative pipeline stages whenever data rates are low. To evaluate our methodology, we designed reconfigurable multiplier-accumulator (MAC) based inverse discrete cosine transform (IDCT) modules for MPEG-2 MP@ML. Our IDCT pipelines were dynamically reconfigurable based on the the number of nonzero coefficients per block and picture size. In comparison with corresponding IDCT implementations that used conventional pipelines, our reconfigurable IDCT modules dissipated about 12-65% less energy.