Low-Routing-Complexity Convolutional/Turbo Decoder Design for Iterative Detection and Decoding Receivers

A highly hardware-shared convolutional/turbo decoder for iterative detection and decoding (IDD) receivers is presented here. Furthermore, parallel dual-mode decoding kernels are proposed to alternatively decode the long-term evolution (LTE)-compatible convolutional codes (CCs) and turbo codes (TCs) using a parity-enhanced soft-input soft-output maximum a-posteriori algorithm. However, decoding the high-constraint-length CC results in complicated interconnections among the parallel decoding kernels and unroutable back-end chip implementation. Therefore, a minimized global route (MGR) design is proposed for the dual-mode decoder to further simplify the global data transfers and reduce the routing complexity. Using a 40-nm CMOS process, the proposed dual-mode decoder achieves a 48% area reduction compared with the individual single-mode TC and single-mode CC decoders. The global routing length of the proposed decoding kernels is reduced by 32% using the MGR design. Because of the feasible placements and routing, the proposed dual-mode decoder is implemented in an application-specific integrated circuit of 2.88-mm 2 core area at the maximum operating frequency of 364 MHz. For the LTE-based IDD receiver, the proposed dual-mode decoder achieves high area efficiencies of 0.21 and 0.35 bits/mm 2 for the TC and CC decoding, respectively.