A system-on-a-chip for pattern recognition architecture and design methodology

A system-on-a-chip for pattern recognition architecture and design methodology

We address in this paper the design and specification of a heterogeneous architecture of a SOC (System-On-a-Chip) for pattern recognition. Once the algorithms involved presented, we investigate the hardware/software codesign methodology, the system architecture and finally the VLSI physical integrat...

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Bibliographische Detailangaben
Hauptverfasser: Aberbour, M., Mehrez, H., Durbin, F., Haussy, J., Lalande, P., Tissot, A.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Computer Science
Coprocessors
Data mining
Design methodology
Frequency
Gabor filters
Hardware Architecture
Information filtering
Information filters
Pattern recognition
System-on-a-chip
Very large scale integration
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Beschreibung
Zusammenfassung:We address in this paper the design and specification of a heterogeneous architecture of a SOC (System-On-a-Chip) for pattern recognition. Once the algorithms involved presented, we investigate the hardware/software codesign methodology, the system architecture and finally the VLSI physical integration. We conclude by giving results on the performance of the system regarding recognition rate and VLSI characteristics.
DOI:10.1109/CAMP.2000.875973