Multiplexed Twin PLLs for Wide-Band FMCW Chirp Generation in 130-nm BiCMOS

We present a pair of fractional-N phase-locked loops (PLLs) followed by a multiplexer (MUX) integrated in one chip. The PLL outputs are multiplexed during chirp generation to increase the frequency modulated continuous wave (FMCW) signal bandwidth to 5GHz around a 31-GHz center frequency. The phase noise measured at the MUX output is −108dBc/Hz at 1-MHz offset from a 31.07-GHz carrier. The chip occupies an area of 1.8 \times 2.1mm 2 . The two PLLs together [excluding the voltage-controlled oscillators (VCOs)] draw 90mA from a 3.3-V supply, while the two VCOs, the MUX, and the output buffers draw 118mA from 2.7V. This array of PLLs offers a solution to improve resolution and precision of FMCW radar systems.