Tutorial: synchronous dynamic memory test construction-a field approach
This paper gives an introduction how to construct dynamic memory tests and test flows. Step by step a basic march test is developed choosing a pattern, voltage levels and timings. Starting with this basic pattern, modifications for characterization, diagnostic and speed testing are discussed. These...
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| creator | Vollrath, J. |
| description | This paper gives an introduction how to construct dynamic memory tests and test flows. Step by step a basic march test is developed choosing a pattern, voltage levels and timings. Starting with this basic pattern, modifications for characterization, diagnostic and speed testing are discussed. These variations are then used to construct a test sequence to ensure functionality according to the data sheet specification. |
| doi_str_mv | 10.1109/MTDT.2000.868616 |
| format | Conference Proceeding |
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| identifier | ISSN: 1087-4852 |
| ispartof | Records of the IEEE International Workshop on Memory Technology, Design and Testing, 2000, p.59-64 |
| issn | 1087-4852 2576-9154 |
| language | eng |
| recordid | cdi_ieee_primary_868616 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Analog circuits Capacitors Circuit testing Logic circuits Logic testing SDRAM Semiconductor device testing Timing Tutorial Voltage |
| title | Tutorial: synchronous dynamic memory test construction-a field approach |
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