A Mixed Topology for Broadband High-Efficiency Doherty Power Amplifier

In this paper, a mixed topology for high efficiency, broadband Doherty power amplifier (DPA) is proposed. The transistor gate biases are set to deep Class-AB for the carrier device and deep Class-C for the peaking device, which enable the DPA to achieve its high efficiency. However, this biasing scheme leads to an inadequate back-off range, which in the past limited applicability. To compensate for this reduced back-off range, a " \pi -type" harmonic injection network (HIN) is integrated into the DPA thereby allowing the second harmonic to be injected between the two active devices. This achieves waveform engineering, which enhances the output power of the peaking amplifier. However, the use of this HIN leads to a reduction in bandwidth due to a mismatch at the fundamental frequency. A bandwidth compensation technique is then proposed, thereby reducing the peaking device drain impedance variation. This mitigates the reduction in bandwidth as a result of the HIN. A high-efficiency DPA is prototyped based on two identical 10-W gallium nitride HEMTs. Measurement results show that a drain efficiency of greater than 60% is achieved at 5.3-6-dB output back-off power from 1.4 to 2.1 GHz.