A simple embedded DRAM process for 0.16-/spl mu/m CMOS technologies
A simple embedded DRAM (eDRAM) process that minimizes the front-end add-on cost is presented for 0.16-/spl mu/m CMOS technologies. The structure results in a low-leakage device (
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| creator | Liu, C.T. Diodato, P.W. Rogers, S. Lai, W.Y.C. Chen, C.J. Lloyd, E.J. Sun, C.Y. Barr, D. Liu, R. Chang, C.P. Trimble, L. Pai, C.S. Vaidya, H. |
| description | A simple embedded DRAM (eDRAM) process that minimizes the front-end add-on cost is presented for 0.16-/spl mu/m CMOS technologies. The structure results in a low-leakage device ( |
| doi_str_mv | 10.1109/VLSIT.2000.852769 |
| format | Conference Proceeding |
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The structure results in a low-leakage device (<20 fA/cell at 100/spl deg/C) suitable for future generations of eDRAMs. Without using poly-Si plugs or metal-0 bit-line runners, topography is identical to the core LOGIC process. Low-temperature MIM capacitors are easily integrated using the W-plugs of metal-2 level. The number of total additional lithographic steps is only 3-5.</description><identifier>ISBN: 0780363051</identifier><identifier>ISBN: 9780780363052</identifier><identifier>DOI: 10.1109/VLSIT.2000.852769</identifier><language>eng</language><publisher>IEEE</publisher><subject>CMOS process ; CMOS technology ; Costs ; FETs ; Furnaces ; Logic devices ; MIM capacitors ; Plugs ; Random access memory ; Surfaces</subject><ispartof>2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. 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The number of total additional lithographic steps is only 3-5.</description><subject>CMOS process</subject><subject>CMOS technology</subject><subject>Costs</subject><subject>FETs</subject><subject>Furnaces</subject><subject>Logic devices</subject><subject>MIM capacitors</subject><subject>Plugs</subject><subject>Random access memory</subject><subject>Surfaces</subject><isbn>0780363051</isbn><isbn>9780780363052</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2000</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNp9jssKgkAUQAci6OUH1Or-gHp9jI-lWFGQBCltxfRahtOIU4v-PqHWrc7iwOEwtrTQsCwMzfMh3WeGjYhGwG3fC0dshn6AjucgtyZMU-o-SHS5y9GesjgC1YiuJSBxoaqiCtanKIGulyUpBbXsYUh7uqm6FsTLFBAnxxSeVN4espXXhtSCjeuiVaT9OGer7SaLd3pDRHnXN6Lo3_l3x_krPxJgN0M</recordid><startdate>2000</startdate><enddate>2000</enddate><creator>Liu, C.T.</creator><creator>Diodato, P.W.</creator><creator>Rogers, S.</creator><creator>Lai, W.Y.C.</creator><creator>Chen, C.J.</creator><creator>Lloyd, E.J.</creator><creator>Sun, C.Y.</creator><creator>Barr, D.</creator><creator>Liu, R.</creator><creator>Chang, C.P.</creator><creator>Trimble, L.</creator><creator>Pai, C.S.</creator><creator>Vaidya, H.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2000</creationdate><title>A simple embedded DRAM process for 0.16-/spl mu/m CMOS technologies</title><author>Liu, C.T. ; Diodato, P.W. ; Rogers, S. ; Lai, W.Y.C. ; Chen, C.J. ; Lloyd, E.J. ; Sun, C.Y. ; Barr, D. ; Liu, R. ; Chang, C.P. ; Trimble, L. ; Pai, C.S. ; Vaidya, H.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_8527693</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2000</creationdate><topic>CMOS process</topic><topic>CMOS technology</topic><topic>Costs</topic><topic>FETs</topic><topic>Furnaces</topic><topic>Logic devices</topic><topic>MIM capacitors</topic><topic>Plugs</topic><topic>Random access memory</topic><topic>Surfaces</topic><toplevel>online_resources</toplevel><creatorcontrib>Liu, C.T.</creatorcontrib><creatorcontrib>Diodato, P.W.</creatorcontrib><creatorcontrib>Rogers, S.</creatorcontrib><creatorcontrib>Lai, W.Y.C.</creatorcontrib><creatorcontrib>Chen, C.J.</creatorcontrib><creatorcontrib>Lloyd, E.J.</creatorcontrib><creatorcontrib>Sun, C.Y.</creatorcontrib><creatorcontrib>Barr, D.</creatorcontrib><creatorcontrib>Liu, R.</creatorcontrib><creatorcontrib>Chang, C.P.</creatorcontrib><creatorcontrib>Trimble, L.</creatorcontrib><creatorcontrib>Pai, C.S.</creatorcontrib><creatorcontrib>Vaidya, H.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Liu, C.T.</au><au>Diodato, P.W.</au><au>Rogers, S.</au><au>Lai, W.Y.C.</au><au>Chen, C.J.</au><au>Lloyd, E.J.</au><au>Sun, C.Y.</au><au>Barr, D.</au><au>Liu, R.</au><au>Chang, C.P.</au><au>Trimble, L.</au><au>Pai, C.S.</au><au>Vaidya, H.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A simple embedded DRAM process for 0.16-/spl mu/m CMOS technologies</atitle><btitle>2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)</btitle><stitle>VLSIT</stitle><date>2000</date><risdate>2000</risdate><spage>60</spage><epage>61</epage><pages>60-61</pages><isbn>0780363051</isbn><isbn>9780780363052</isbn><abstract>A simple embedded DRAM (eDRAM) process that minimizes the front-end add-on cost is presented for 0.16-/spl mu/m CMOS technologies. The structure results in a low-leakage device (<20 fA/cell at 100/spl deg/C) suitable for future generations of eDRAMs. Without using poly-Si plugs or metal-0 bit-line runners, topography is identical to the core LOGIC process. Low-temperature MIM capacitors are easily integrated using the W-plugs of metal-2 level. The number of total additional lithographic steps is only 3-5.</abstract><pub>IEEE</pub><doi>10.1109/VLSIT.2000.852769</doi></addata></record> |
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| identifier | ISBN: 0780363051 |
| ispartof | 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104), 2000, p.60-61 |
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| language | eng |
| recordid | cdi_ieee_primary_852769 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | CMOS process CMOS technology Costs FETs Furnaces Logic devices MIM capacitors Plugs Random access memory Surfaces |
| title | A simple embedded DRAM process for 0.16-/spl mu/m CMOS technologies |
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