Embedded DRAM: an element and circuit evaluation

Embedded DRAM memory cells employing advanced capacitor dielectrics (Ta/sub 2/O/sub 5/) have been designed, fabricated, and measured. Memory cell data retention time is used to compare capacitor characteristics between four Ta/sub 2/O/sub 5/ equipment vendors. Static behavior in one type of DRAM cel...

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Hauptverfasser:	Diodato, P.W., O'Neill, J.H., Wong, Y.-H., Alers, G.B., Vaidya, H.M., Chaudhry, S., Lindenberger, W.S., Dumbri, A.C., Liu, C.-T., Lai, W.Y.-C.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Application specific integrated circuits High-K gate dielectrics Integrated circuit interconnections Isolation technology Message-oriented middleware MOS capacitors Random access memory Surfaces Transistors Tungsten
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Beschreibung
Zusammenfassung:	Embedded DRAM memory cells employing advanced capacitor dielectrics (Ta/sub 2/O/sub 5/) have been designed, fabricated, and measured. Memory cell data retention time is used to compare capacitor characteristics between four Ta/sub 2/O/sub 5/ equipment vendors. Static behavior in one type of DRAM cell is attributed to the bimodal current-voltage characteristic of the Ta/sub 2/O/sub 5/, and circuit topography.
DOI:	10.1109/CICC.2000.852669