A million gate PLD with 622 MHz I/O interface, multiple PLLs and high performance embedded CAM

A million gate PLD with 622 MHz I/O interface, multiple PLLs and high performance embedded CAM

A million gate programmable logic device (PLD) designed for high performance system integration is discussed. The APEX 20K1000E is fabricated on a 0.18 /spl mu/m CMOS process. The chip supports multiple I/O standards with data bandwidth up to 622 Mbps when using the integrated low voltage differenti...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Cheung, S., Chua, K.K., Ang, B.J., Chong, T.P., Goay, W.L., Koay, W.Y., Kuan, S.W., Lim, C.P., Oon, J.S., See, T.T., Sung, C., Tan, K.P., Tan, Y.F., Wong, C.K.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Associative memory
Bandwidth
CADCAM
Clocks
CMOS process
Computer aided manufacturing
Low voltage
Phase locked loops
Programmable logic devices
Signal synthesis
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A million gate programmable logic device (PLD) designed for high performance system integration is discussed. The APEX 20K1000E is fabricated on a 0.18 /spl mu/m CMOS process. The chip supports multiple I/O standards with data bandwidth up to 622 Mbps when using the integrated low voltage differential signaling (LVDS) interfaces. Multiple on-chip phase-locked loops (PLL) increase performance and provide clock-frequency synthesis. The embedded content addressable memory (CAM) enhances performance for fast search applications.
DOI:10.1109/CICC.2000.852636