Memristor-Based Hybrid Fault Tolerant Structure With Concurrent Reconfigurability

Fault tolerance is one of the main issues of electronic devices especially for controlling and monitoring of the operations in extreme environments. In this letter, a new memristor-based hybrid approach has been proposed, which combines attractive features of the both static and dynamic methods to introduce a new concurrent reconfigurable structure. The simulation results show that the proposed structure tolerates transient and permanent faults during the run-time with minimum delay, power consumption, and area overhead in comparison to the related works. The proposed work also reaches to minimum silicon protection factor with zero pause time during fault recovery phase.