High-speed demonstration of a superconducting pseudo-random bit-sequence generator

This paper describes the design, analysis and test results for a 4-bit pseudo-random bit-sequence generator (PRBSG) implemented with complementary output switching logic (COSL) gates. The PRBSG was optimized using a Monte Carlo simulation method for 10-GHz operation. The circuit has been fabricated...

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Veröffentlicht in:	IEEE transactions on applied superconductivity 2000-06, Vol.10 (2), p.1593-1597
Hauptverfasser:	Wang, Z., Jeffery, M.J., Perold, W.J., Van Duzer, T.
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Circuit testing Computer simulation Critical current density Electrical resistivity Electronics Energy consumption Exact sciences and technology Gates (circuits) Generators High speed Integrated circuits Integrated circuits by function (including memories and processors) Logic design Logic gates Logic testing Monte Carlo methods Niobium Optimization methods Power consumption Power supplies Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Superconducting devices Superconducting logic circuits Superconductivity
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Beschreibung
Zusammenfassung:	This paper describes the design, analysis and test results for a 4-bit pseudo-random bit-sequence generator (PRBSG) implemented with complementary output switching logic (COSL) gates. The PRBSG was optimized using a Monte Carlo simulation method for 10-GHz operation. The circuit has been fabricated using niobium technology with critical current density of 1 kA/cm/sup 2/ and sheet resistance of 1 /spl Omega//sq. The 4-bit PRBSG consists of 12 gates and its area is 1530/spl times/950 /spl mu/m/sup 2/. It has been fully tested with a three-phase power supply, and its power consumption is 0.15 mW. The correct operations have been verified experimentally at clock frequencies of up to 2 GHz.
ISSN:	1051-8223 1558-2515
DOI:	10.1109/77.848306