Write Disturb in Ferroelectric FETs and Its Implication for 1T-FeFET AND Memory Arrays

In this letter, the write disturb of Hf 0.5 Zr 0.5 O 2 -based 1T-FeFET nonvolatile AND memory array is experimentally investigated for {V}_{W} /2 and {V}_{W} /3 inhibition bias schemes to determine the worst-case memory sensing condition. Read margin analysis reveals that the increased leakage current in the low- {V}_{\textsf {TH}} erased state and the increased read current of the high- {V}_{\textsf {TH}} programmed state are the key factors that limit the maximum array size.