Nonuniformly Distributed Electronic Impedance Synthesizer

Benefiting from advantageous features of fast tuning, small size, and easy integration, the electronic impedance synthesizer (EIS) has been developed for on-wafer load-pull characterization systems, tunable matching networks, reconfigurable devices and systems, and so on. The previous designs of the EIS were mostly based on the empirical data instead of a closed-form design. Moreover, incomplete figures of merit (FOM) were chosen to optimize and evaluate the EIS. In this paper, we propose and present, first of all, a semiclosed-form design procedure for the distributed EIS. Then, a particle swarm optimization method is introduced to optimize the proposed nonuniformly distributed EIS, which comprises an adjusting circuit and a nonuniformly distributed circuit. Experimental results demonstrate that the proposed nonuniformly distributed structure can not only improve the Smith chart coverage but also reduce the size, compared to the uniform counterpart. The fabricated nonuniform EIS operating from 0.8 to 2.5 GHz, exhibits a good agreement between theory and measurement. Furthermore, the most comprehensive FOM are presented to evaluate the fabricated EIS.