RF Performance of a Highly Linear Power Amplifier EDNMOS Transistor on Trap-Rich SOI

Results specific to power amplifiers (PAs) designed using a SOI EDNMOS transistor free of kinks in ID-VD plane and high breakdown voltage are presented. The suppression of the drain current kink and improvement in breakdown voltage are achieved by the omission of the N + source implant step. Instead, the source junction is realized by an optimized NLDD implant step only, allowing the formation of an under-source body contact. This approach is highly suitable for integration with RF switch and low-noise amplifiers on the same thin film SOI substrate. The improved channel conductance is found to give rise to highly linear amplitude and phase characteristics under high power conditions when the optimized EDNMOS device is used standalone as a PA.