Parametric fault simulation and test vector generation

Process variation has forever been the major fail cause of analog circuits where small deviations in component values cause large deviations in the measured output parameters. This paper presents a new approach for parametric fault simulation and test vector generation. The proposed approach utilizes the process information and the sensitivity of the circuit principal components in order to generate statistical models of the fault-free and the faulty circuit. The obtained information is then used as a measurement to quantify the testability of the circuit. This approach, extended by hard fault testing, has been implemented as automated tool set for IC testing called FaultMaxx and TestMaxx.