Layout-oriented synthesis of high performance analog circuits

Layout-oriented synthesis of high performance analog circuits

This paper presents a methodology for the synthesis of high performance analog circuits. Layout parasitics are estimated and compensated during circuit sizing. Physical layout constraints are thus taken into consideration early in the design. This approach shortens the overall design time by avoidin...

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Hauptverfasser: Dessouky, M., Louerat, M.-M., Porte, J.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Analog circuits
Automatic control
Circuit optimization
Circuit synthesis
Computer Science
Coupling circuits
Degradation
Design optimization
Electrical capacitance tomography
Parasitic capacitance
Process design
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Beschreibung
Zusammenfassung:This paper presents a methodology for the synthesis of high performance analog circuits. Layout parasitics are estimated and compensated during circuit sizing. Physical layout constraints are thus taken into consideration early in the design. This approach shortens the overall design time by avoiding laborious sizing-layout iterations. The approach has been implemented using two knowledge-based tools dedicated to analog circuit sizing and layout generation. An example of a high performance OTA is presented to illustrate the effectiveness of the approach.
DOI:10.1109/DATE.2000.840015