SC implementation of FIR filters for digital communication systems

SC implementation of FIR filters for digital communication systems

In this paper a Switched-Capacitor (SC) architecture for the processing of binary input signals is presented. The architecture is especially useful for the realization of Finite Impulse Response (FIR) filters. A 23-th order Raised-Cosine (RC) filter employing 11 capacitors is designed. The filter ha...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Rocha-Perez, J.M., Silva-Martinez, J.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Capacitors
Delay
Digital communication
Digital filters
Equations
Finite impulse response filter
Information filtering
Information filters
Optical filters
Switches
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:In this paper a Switched-Capacitor (SC) architecture for the processing of binary input signals is presented. The architecture is especially useful for the realization of Finite Impulse Response (FIR) filters. A 23-th order Raised-Cosine (RC) filter employing 11 capacitors is designed. The filter has been simulated using a 0.8 /spl mu/m analog CMOS process. Hspice results have shown the feasibility of the proposed design technique.
DOI:10.1109/MMICA.1999.833629