Bit-Level Load Balancing: A New Technique for Improving the Write Throughput of Deeply Scaled STT-MRAM

Emerging non-volatile memories (NVMs) have drawn significant attention as potential DRAM replacements. STT-MRAM is one of the most promising NVMs due to its relatively low write energy, high speed, and high endurance. However, STT-MRAM suffers from its own scaling problems. As the size of the access transistor is decreased to reduce the cell area, the magnitude of the switching current that is supplied to the storage element decreases. The reduced switching current significantly lengthens the switching time, which makes write throughput a significant performance bottleneck for a memory system constructed from dense STT-MRAM cells. We introduce bit-level load balancing, a new technique that mitigates the performance overhead of limited write throughput in high-density, STT-MRAM based main memories. Bit-level load balancing takes advantage of the observation that many of the bits within a row of STT-MRAM remain unchanged when performing a write. The key idea is to architect the memory system such that different columns of different rows can be simultaneously written to an STT-MRAM subarray. By interleaving in time the bit updates from multiple writes, bit level load balancing improves average system performance by 19 percent, and comes within 6 percent of the performance of a DRAM based system.