RF potential of a 0.18-/spl mu/m CMOS logic device technology

The radio-frequency (RF) performance of a 0.18-/spl mu/m CMOS logic technology is assessed by evaluating the cutoff and maximum oscillation frequencies (f/sub T/ and f/sub max/), the minimum noise figure (F/sub min/) and associated power gain (G/sub a/), and the 1/f noise of the devices. Gate-biasing and channel-length and gate-finger-length adjustments are identified as means to optimize the RF performance without any technology process modifications. Changing to N/sub 2/O gate dielectrics is shown to greatly reduce the 1/f noise without sacrificing the AC performance. The power amplifier characteristics of CMOS at low power levels are also discussed.