A novel trench DRAM cell with a vertical access transistor and buried strap (VERI BEST) for 4 Gb/16 Gb

Results are presented for a novel trench capacitor DRAM cell using a vertical access transistor along the storage trench sidewall which effectively decouples the gate length from the lithographic groundrule. A unique feature of this cell is the vertical access transistor in the array which is self-a...

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Bibliographische Detailangaben
Hauptverfasser:	Gruening, U., Radens, C.J., Mandelman, J.A., Michaelis, A., Seitz, M., Arnold, N., Lea, D., Casarotto, D., Knorr, A., Halle, S., Ivers, T.H., Economikos, L., Kudelka, S., Rahn, S., Tews, H., Lee, H., Divakaruni, R., Welser, J.J., Furukawa, T., Kanarsky, T.S., Alsmeier, J., Bronner, G.B.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Capacitors Doping Etching Microelectronics MOSFET circuits Random access memory Research and development Testing Threshold voltage Transistors
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Beschreibung
Zusammenfassung:	Results are presented for a novel trench capacitor DRAM cell using a vertical access transistor along the storage trench sidewall which effectively decouples the gate length from the lithographic groundrule. A unique feature of this cell is the vertical access transistor in the array which is self-aligned to the buried strap connection of the storage trench (VERI BEST) and bounded by trench isolation oxide. The VERI BEST cell concept, process and electrical results obtained from 8F/sup 2/ test cell arrays at 0.175 /spl mu/m groundrules are described in this paper.
DOI:	10.1109/IEDM.1999.823838