A design of 2-D DCT/IDCT for real-time video applications

In this paper, we present the implementation of the 2-D DCT/IDCT that is capable of processing an 8/spl times/8 pixel block and satisfies the accuracy specification of ITU-T. This circuit was designed for real-time processing of 33 MHz sample rate video data. It uses row-column decomposition to implement a two dimensional transform. Distributed arithmetic combined with bit-serial and bit-parallel structures is used to implement the required vector inner product concurrently. The resultant circuit only uses memory and shift registers, and adders. No multipliers are required. The circuit has been laid out using a 0.5 /spl mu/m CMOS technology, and contains 10000 gates approximately and 64/spl times/16 bit memory.