On-chip wiring design challenges for GHz operation

On-chip wiring design challenges for GHz operation

This presentation reviews current on-chip wiring design practices and the fundamental properties of on-chip lossy transmission lines. The deficiencies of RC-circuit representation are highlighted and it is shown that many of the modeling and simulation techniques developed for package interconnectio...

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Bibliographische Detailangaben
Hauptverfasser: Deutsch, A., Smith, H., Kopcsay, G.V., Edelstein, D.C., Coteus, P.W.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuit noise
Clocks
Crosstalk
Driver circuits
Integrated circuit interconnections
Packaging
Propagation delay
RLC circuits
System-on-a-chip
Wiring
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Beschreibung
Zusammenfassung:This presentation reviews current on-chip wiring design practices and the fundamental properties of on-chip lossy transmission lines. The deficiencies of RC-circuit representation are highlighted and it is shown that many of the modeling and simulation techniques developed for package interconnections must be adopted by microprocessor designers in order to achieve GHz clock rates.
DOI:10.1109/EPEP.1999.819190