A simulator-optimizer for the design of very low phase noise CMOS LC-oscillators
A simulator-optimizer program for spiral inductors on silicon substrates is presented. The program implements the three-dimensional inductance extraction program FastHenry in a simulated annealing optimization loop. The simulated annealing algorithm performs the optimization of automatically generat...
Gespeichert in:
| Hauptverfasser: | , , , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 1560 vol.3 |
|---|---|
| container_issue | |
| container_start_page | 1557 |
| container_title | |
| container_volume | 3 |
| creator | De Muer, B. De Ranter, C. Crols, J. Steyaert, M. |
| description | A simulator-optimizer program for spiral inductors on silicon substrates is presented. The program implements the three-dimensional inductance extraction program FastHenry in a simulated annealing optimization loop. The simulated annealing algorithm performs the optimization of automatically generated spiral inductor geometries towards an optimal quality factor for a specified technology. Using the program, a low-phase-noise LC-tank Voltage Controlled Oscillator (VCO) is integrated in a 0.65 /spl mu/m BiCMOS process. The phase noise is as low as -127.5 dBc/Hz at an offset frequency of 600 kHz from a 1.33 GHz carrier, while consuming only 10 mA from a 2 V power supply. |
| doi_str_mv | 10.1109/ICECS.1999.814468 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_814468</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>814468</ieee_id><sourcerecordid>814468</sourcerecordid><originalsourceid>FETCH-LOGICAL-i87t-4cd3215ab8911868c33c8f9afd1df69a77c29d03dcf43178495761b1ae1e032a3</originalsourceid><addsrcrecordid>eNotj8tKAzEYRgMiVGsfoK7yAjPmn8zksiyhamGkQrsvaS42MtMMyajUp7e0fotzdgc-hOZASgAin1ZqqTYlSClLAXXNxA26J1wQ2jBRyQma5fxJzmsaUTF2h94XOIf-q9NjTEUcxtCHX5ewjwmPB4ety-HjiKPH3y6dcBd_8HDQ2eFjDGeqt_UGt6qI2YTu0sgP6NbrLrvZv6do-7zcqteiXb-s1KItguBjURtLK2j0XkgAwYSh1AgvtbdgPZOac1NJS6g1vqbARS0bzmAP2oEjtNJ0ih6v2eCc2w0p9DqddtfL9A-VsEyK</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A simulator-optimizer for the design of very low phase noise CMOS LC-oscillators</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>De Muer, B. ; De Ranter, C. ; Crols, J. ; Steyaert, M.</creator><creatorcontrib>De Muer, B. ; De Ranter, C. ; Crols, J. ; Steyaert, M.</creatorcontrib><description>A simulator-optimizer program for spiral inductors on silicon substrates is presented. The program implements the three-dimensional inductance extraction program FastHenry in a simulated annealing optimization loop. The simulated annealing algorithm performs the optimization of automatically generated spiral inductor geometries towards an optimal quality factor for a specified technology. Using the program, a low-phase-noise LC-tank Voltage Controlled Oscillator (VCO) is integrated in a 0.65 /spl mu/m BiCMOS process. The phase noise is as low as -127.5 dBc/Hz at an offset frequency of 600 kHz from a 1.33 GHz carrier, while consuming only 10 mA from a 2 V power supply.</description><identifier>ISBN: 0780356829</identifier><identifier>ISBN: 9780780356825</identifier><identifier>DOI: 10.1109/ICECS.1999.814468</identifier><language>eng</language><publisher>IEEE</publisher><subject>Geometry ; Inductance ; Inductors ; Phase noise ; Q factor ; Silicon ; Simulated annealing ; Solid modeling ; Spirals ; Voltage-controlled oscillators</subject><ispartof>ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357), 1999, Vol.3, p.1557-1560 vol.3</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/814468$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2056,4047,4048,27923,54918</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/814468$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>De Muer, B.</creatorcontrib><creatorcontrib>De Ranter, C.</creatorcontrib><creatorcontrib>Crols, J.</creatorcontrib><creatorcontrib>Steyaert, M.</creatorcontrib><title>A simulator-optimizer for the design of very low phase noise CMOS LC-oscillators</title><title>ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357)</title><addtitle>ICECS</addtitle><description>A simulator-optimizer program for spiral inductors on silicon substrates is presented. The program implements the three-dimensional inductance extraction program FastHenry in a simulated annealing optimization loop. The simulated annealing algorithm performs the optimization of automatically generated spiral inductor geometries towards an optimal quality factor for a specified technology. Using the program, a low-phase-noise LC-tank Voltage Controlled Oscillator (VCO) is integrated in a 0.65 /spl mu/m BiCMOS process. The phase noise is as low as -127.5 dBc/Hz at an offset frequency of 600 kHz from a 1.33 GHz carrier, while consuming only 10 mA from a 2 V power supply.</description><subject>Geometry</subject><subject>Inductance</subject><subject>Inductors</subject><subject>Phase noise</subject><subject>Q factor</subject><subject>Silicon</subject><subject>Simulated annealing</subject><subject>Solid modeling</subject><subject>Spirals</subject><subject>Voltage-controlled oscillators</subject><isbn>0780356829</isbn><isbn>9780780356825</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1999</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj8tKAzEYRgMiVGsfoK7yAjPmn8zksiyhamGkQrsvaS42MtMMyajUp7e0fotzdgc-hOZASgAin1ZqqTYlSClLAXXNxA26J1wQ2jBRyQma5fxJzmsaUTF2h94XOIf-q9NjTEUcxtCHX5ewjwmPB4ety-HjiKPH3y6dcBd_8HDQ2eFjDGeqt_UGt6qI2YTu0sgP6NbrLrvZv6do-7zcqteiXb-s1KItguBjURtLK2j0XkgAwYSh1AgvtbdgPZOac1NJS6g1vqbARS0bzmAP2oEjtNJ0ih6v2eCc2w0p9DqddtfL9A-VsEyK</recordid><startdate>1999</startdate><enddate>1999</enddate><creator>De Muer, B.</creator><creator>De Ranter, C.</creator><creator>Crols, J.</creator><creator>Steyaert, M.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1999</creationdate><title>A simulator-optimizer for the design of very low phase noise CMOS LC-oscillators</title><author>De Muer, B. ; De Ranter, C. ; Crols, J. ; Steyaert, M.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i87t-4cd3215ab8911868c33c8f9afd1df69a77c29d03dcf43178495761b1ae1e032a3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1999</creationdate><topic>Geometry</topic><topic>Inductance</topic><topic>Inductors</topic><topic>Phase noise</topic><topic>Q factor</topic><topic>Silicon</topic><topic>Simulated annealing</topic><topic>Solid modeling</topic><topic>Spirals</topic><topic>Voltage-controlled oscillators</topic><toplevel>online_resources</toplevel><creatorcontrib>De Muer, B.</creatorcontrib><creatorcontrib>De Ranter, C.</creatorcontrib><creatorcontrib>Crols, J.</creatorcontrib><creatorcontrib>Steyaert, M.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>De Muer, B.</au><au>De Ranter, C.</au><au>Crols, J.</au><au>Steyaert, M.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A simulator-optimizer for the design of very low phase noise CMOS LC-oscillators</atitle><btitle>ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357)</btitle><stitle>ICECS</stitle><date>1999</date><risdate>1999</risdate><volume>3</volume><spage>1557</spage><epage>1560 vol.3</epage><pages>1557-1560 vol.3</pages><isbn>0780356829</isbn><isbn>9780780356825</isbn><abstract>A simulator-optimizer program for spiral inductors on silicon substrates is presented. The program implements the three-dimensional inductance extraction program FastHenry in a simulated annealing optimization loop. The simulated annealing algorithm performs the optimization of automatically generated spiral inductor geometries towards an optimal quality factor for a specified technology. Using the program, a low-phase-noise LC-tank Voltage Controlled Oscillator (VCO) is integrated in a 0.65 /spl mu/m BiCMOS process. The phase noise is as low as -127.5 dBc/Hz at an offset frequency of 600 kHz from a 1.33 GHz carrier, while consuming only 10 mA from a 2 V power supply.</abstract><pub>IEEE</pub><doi>10.1109/ICECS.1999.814468</doi></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISBN: 0780356829 |
| ispartof | ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357), 1999, Vol.3, p.1557-1560 vol.3 |
| issn | |
| language | eng |
| recordid | cdi_ieee_primary_814468 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Geometry Inductance Inductors Phase noise Q factor Silicon Simulated annealing Solid modeling Spirals Voltage-controlled oscillators |
| title | A simulator-optimizer for the design of very low phase noise CMOS LC-oscillators |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-13T12%3A28%3A56IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20simulator-optimizer%20for%20the%20design%20of%20very%20low%20phase%20noise%20CMOS%20LC-oscillators&rft.btitle=ICECS'99.%20Proceedings%20of%20ICECS%20'99.%206th%20IEEE%20International%20Conference%20on%20Electronics,%20Circuits%20and%20Systems%20(Cat.%20No.99EX357)&rft.au=De%20Muer,%20B.&rft.date=1999&rft.volume=3&rft.spage=1557&rft.epage=1560%20vol.3&rft.pages=1557-1560%20vol.3&rft.isbn=0780356829&rft.isbn_list=9780780356825&rft_id=info:doi/10.1109/ICECS.1999.814468&rft_dat=%3Cieee_6IE%3E814468%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=814468&rfr_iscdi=true |