A 1.1- \mu \text 33-Mpixel 240-fps 3-D-Stacked CMOS Image Sensor With Three-Stage Cyclic-Cyclic-SAR Analog-to-Digital Converters

In this paper, a 1.1-μm-pitch 33-Mpixel 240-fps backside-illuminated 3-D-stacked CMOS image sensor with three-stage cyclic-cyclic-successive-approximation-register (SAR) analog-to-digital converters (ADCs) is developed. The narrow-pitch interconnection technology that connects the pixels and arrayed ADCs inside the pixel area is described. The 3-D-stacked architecture, constructed using the interconnection technology, makes it possible to place a 1932 (H) × 4 (V) correlated-double-sampling/ADC array underneath the pixel area. Furthermore, the pipelined and parallel operation of the three-stage cyclic-cyclic-SAR ADC architecture effectively reduces the conversion time period and power consumption and achieves 12-b precision within one horizontal scan time of 0.92 μs. As a result, the interconnection technology and ADC architecture achieved a high frame rate of 240 fps in 33 Mpixels. Random noise of 3.6 e- and low power consumption of 3.0 W were attained at an extremely high pixel rate of 7.96 Gpixel/s. A good figure of merit is achieved compared with recently developed image sensors.