A high-performance two-stage packet switch architecture

A high-performance two-stage packet switch architecture

This paper contributes a distributed packet controller which reduces queueing to a single stage in two-stage packet switches. Software and neural network based controllers are described. Simulations under a range of traffic conditions for a 1024/spl times/1024 switch size shows the simplest architec...

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Veröffentlicht in:IEEE transactions on communications 1999-12, Vol.47 (12), p.1792-1795
1. Verfasser: Brown, T.X.
Format: Artikel
Sprache:eng
Schlagworte:
Architecture
Asynchronous transfer mode
Communication system traffic control
Computer architecture
Computer programs
Computer simulation
Distributed control
Neural networks
Neurons
Packet switching
Single stage
Software
Switches
Throughput
Traffic control
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Beschreibung
Zusammenfassung:This paper contributes a distributed packet controller which reduces queueing to a single stage in two-stage packet switches. Software and neural network based controllers are described. Simulations under a range of traffic conditions for a 1024/spl times/1024 switch size shows the simplest architecture has the best performance.
ISSN:0090-6778
1558-0857
DOI:10.1109/26.809698