SOI implementation of a 64-bit adder

SOI implementation of a 64-bit adder

Silicon-On-Insulator (SOI) technology allows for high performance by eliminating latch up in bulk CMOS, improving the short-channel effect, and soft error immunity. However, the floating body effect in SOI devices and the resulting hysteresis poses major challenges for dynamic circuit designers. In...

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Bibliographische Detailangaben
Hauptverfasser: Tran, J.V., Mounes-Toussi, F., Storino, S.N., Stasiak, D.L.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Adders
CMOS technology
Copper
Integrated circuit interconnections
Microprocessors
Output feedback
State feedback
Switches
Switching circuits
Voltage
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Beschreibung
Zusammenfassung:Silicon-On-Insulator (SOI) technology allows for high performance by eliminating latch up in bulk CMOS, improving the short-channel effect, and soft error immunity. However, the floating body effect in SOI devices and the resulting hysteresis poses major challenges for dynamic circuit designers. In this paper, we describe implementation of a 64-bit adder and some of the techniques used to overcome the parasitic bipolar discharge effect while maintaining performance.
ISSN:1063-6404
2576-6996
DOI:10.1109/ICCD.1999.808598