A Low Noise Low Offset Readout Circuit for Magnetic-Random-Access-Memory

A Low Noise Low Offset Readout Circuit for Magnetic-Random-Access-Memory

A unique readout circuit topology aimed at integration with a novel type of magnetic random access memory (MRAM) is presented. The properties of the new MRAM bitcell are introduced, and the specifics of the circuit used to interface with the CMOS circuitry are described. The noise transfer function...

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Veröffentlicht in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2018-04, Vol.65 (4), p.1224-1233
Hauptverfasser: Mordakhay, Anatoli, Telepinsky, Yevgeniy, Klein, Lior, Shor, Joseph, Fish, Alexander
Format: Artikel
Sprache:eng
Schlagworte:
Capacitors
Circuit topology
Circuits
CMOS
Computer memory
Low noise
Magnetic circuits
Magnetic properties
Magnetization
Memory
MRAM
Noise
non-volatile memory (NVM)
Random access memory
sense amplifier
Switches
Thermal noise
Topology
Transfer functions
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Beschreibung
Zusammenfassung:A unique readout circuit topology aimed at integration with a novel type of magnetic random access memory (MRAM) is presented. The properties of the new MRAM bitcell are introduced, and the specifics of the circuit used to interface with the CMOS circuitry are described. The noise transfer function and effectiveness of the proposed topology with its practical limitations are discussed. Post-silicon measurement results verify the validity of this topology. Integration of the proposed readout circuit with the MRAM bitcells is discussed. Measurement results show an integrated input noise of 89~\mu Vrms, and reliable sensing of signal level of 1 mV.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2017.2743045