Interdie Coupling Extraction and Physical Design Optimization for Face-to-Face 3-D ICs

Interdie coupling in face-to-face-bonded three-dimensional (3-D) ICs is becoming increasingly important for power and signal integrity. For the first time, we conduct a comprehensive study of the coupling impact in all three aspects: extraction methodology, physical design, and technology scaling. We conduct detailed sensitivity analysis of key parameters using full-chip 3-D IC designs built across multiple technologies from 28 nm down to 7 nm. First, we develop a hierarchy-aware design methodology that reduces the total wirelength by 28.1% and interdie coupling by 27.5%. Second, results show that interdie capacitance significantly affects full-chip timing and noise across multiple technology generations. Specifically, clock delay increases by 18% and skew 16%. Moreover, an additional power distribution network (PDN) layer in the 3-D design further reduces interdie coupling by 66%. Third, interdie coupling remains similar in advanced nodes with die-to-die distance scaling. Finally, our extraction methodology named context creation developed to handle design space exploration for logic-memory stacking reduces extraction error to 0.41% and timing error to 0.16%.