Highly testable finite state machines based on EXOR logic

It is well-known that AND/EXOR circuits are more easily testable than AND/OR circuits. Therefore, in this paper, we primarily propose to use AND/EXOR realizations for implementation of the combinational logic parts of finite state machines. Then, we investigate the effect of different state assignments (i.e. one-hot, grey-code, etc.) and that of using different types of registers (i.e. D-type, JK-type, etc) on the testability of finite state machines. As the basis of our measurements, we considered two easily testable AND/EXOR realizations; one for EXOR sum-of-products expressions and the other for generalized Reed-Muller expressions. We make comparisons of these realizations in terms of area and the number of test patterns as we change the state assignment and the type of registers. We also show that 2-level AND/EXOR realizations can yield less area than 2-level AND/OR realizations in the implementation of finite state machines.