Analysis of Short-Channel Effects in Junctionless DG MOSFETs
This brief investigates short-channel effects (SCEs) in junctionless (JL) double-gate (DG) MOSFETs analytically by solving the 2-D potential in subthreshold. Ids-Vg curves and Vt rolloff generated from the model are validated by 2-D numerical simulations (Technology Computer Aided Design). It is sho...
Gespeichert in:
| Veröffentlicht in: | IEEE transactions on electron devices 2017-08, Vol.64 (8), p.3511-3514 |
|---|---|
| Hauptverfasser: | , , |
| Format: | Artikel |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 3514 |
|---|---|
| container_issue | 8 |
| container_start_page | 3511 |
| container_title | IEEE transactions on electron devices |
| container_volume | 64 |
| creator | Xie, Qian Wang, Zheng Taur, Yuan |
| description | This brief investigates short-channel effects (SCEs) in junctionless (JL) double-gate (DG) MOSFETs analytically by solving the 2-D potential in subthreshold. Ids-Vg curves and Vt rolloff generated from the model are validated by 2-D numerical simulations (Technology Computer Aided Design). It is shown that the SCE of JL MOSFETs is inherently worse than that of undoped DG MOSFETs. The SCE worsens with increasing doping concentration in the channel. |
| doi_str_mv | 10.1109/TED.2017.2716969 |
| format | Article |
| fullrecord | <record><control><sourceid>crossref_RIE</sourceid><recordid>TN_cdi_ieee_primary_7987855</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>7987855</ieee_id><sourcerecordid>10_1109_TED_2017_2716969</sourcerecordid><originalsourceid>FETCH-LOGICAL-c263t-12bfa4cd5c70f6897046233bc16f3f55cacf858bf9ae74fb02be59bebae3fb733</originalsourceid><addsrcrecordid>eNo9j01Lw0AYhBdRMFbvgpf9A4n7_QFeShurUumh9bzsrvvSSEwkGw_996a0eBpmmBl4ELqnpKKU2MddvawYobpimiqr7AUqqJS6tEqoS1QQQk1pueHX6Cbnr8kqIViBnuadbw-5ybgHvN33w1gu9r7rUotrgBTHjJsOv_12cWz6rk054-UKv2-2z_Uu36Ir8G1Od2edoY8pXryU683qdTFfl5EpPpaUBfAifsqoCShjNRGKcR4iVcBByugjGGkCWJ-0gEBYSNKGFHziEDTnM0ROv3Hocx4SuJ-h-fbDwVHijvRuondHenemnyYPp0mTUvqva2u0kZL_AZLUVcc</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype></control><display><type>article</type><title>Analysis of Short-Channel Effects in Junctionless DG MOSFETs</title><source>IEEE</source><creator>Xie, Qian ; Wang, Zheng ; Taur, Yuan</creator><creatorcontrib>Xie, Qian ; Wang, Zheng ; Taur, Yuan</creatorcontrib><description>This brief investigates short-channel effects (SCEs) in junctionless (JL) double-gate (DG) MOSFETs analytically by solving the 2-D potential in subthreshold. Ids-Vg curves and Vt rolloff generated from the model are validated by 2-D numerical simulations (Technology Computer Aided Design). It is shown that the SCE of JL MOSFETs is inherently worse than that of undoped DG MOSFETs. The SCE worsens with increasing doping concentration in the channel.</description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/TED.2017.2716969</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>IEEE</publisher><subject>Analytical models ; Doping ; Double gate (DG) ; Electric potential ; junctionless (JL) ; Logic gates ; MOSFET ; MOSFETS ; Semiconductor device modeling ; short-channel effects (SCEs) ; Silicon</subject><ispartof>IEEE transactions on electron devices, 2017-08, Vol.64 (8), p.3511-3514</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c263t-12bfa4cd5c70f6897046233bc16f3f55cacf858bf9ae74fb02be59bebae3fb733</citedby><cites>FETCH-LOGICAL-c263t-12bfa4cd5c70f6897046233bc16f3f55cacf858bf9ae74fb02be59bebae3fb733</cites><orcidid>0000-0002-5232-0298</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/7987855$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/7987855$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Xie, Qian</creatorcontrib><creatorcontrib>Wang, Zheng</creatorcontrib><creatorcontrib>Taur, Yuan</creatorcontrib><title>Analysis of Short-Channel Effects in Junctionless DG MOSFETs</title><title>IEEE transactions on electron devices</title><addtitle>TED</addtitle><description>This brief investigates short-channel effects (SCEs) in junctionless (JL) double-gate (DG) MOSFETs analytically by solving the 2-D potential in subthreshold. Ids-Vg curves and Vt rolloff generated from the model are validated by 2-D numerical simulations (Technology Computer Aided Design). It is shown that the SCE of JL MOSFETs is inherently worse than that of undoped DG MOSFETs. The SCE worsens with increasing doping concentration in the channel.</description><subject>Analytical models</subject><subject>Doping</subject><subject>Double gate (DG)</subject><subject>Electric potential</subject><subject>junctionless (JL)</subject><subject>Logic gates</subject><subject>MOSFET</subject><subject>MOSFETS</subject><subject>Semiconductor device modeling</subject><subject>short-channel effects (SCEs)</subject><subject>Silicon</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2017</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9j01Lw0AYhBdRMFbvgpf9A4n7_QFeShurUumh9bzsrvvSSEwkGw_996a0eBpmmBl4ELqnpKKU2MddvawYobpimiqr7AUqqJS6tEqoS1QQQk1pueHX6Cbnr8kqIViBnuadbw-5ybgHvN33w1gu9r7rUotrgBTHjJsOv_12cWz6rk054-UKv2-2z_Uu36Ir8G1Od2edoY8pXryU683qdTFfl5EpPpaUBfAifsqoCShjNRGKcR4iVcBByugjGGkCWJ-0gEBYSNKGFHziEDTnM0ROv3Hocx4SuJ-h-fbDwVHijvRuondHenemnyYPp0mTUvqva2u0kZL_AZLUVcc</recordid><startdate>201708</startdate><enddate>201708</enddate><creator>Xie, Qian</creator><creator>Wang, Zheng</creator><creator>Taur, Yuan</creator><general>IEEE</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><orcidid>https://orcid.org/0000-0002-5232-0298</orcidid></search><sort><creationdate>201708</creationdate><title>Analysis of Short-Channel Effects in Junctionless DG MOSFETs</title><author>Xie, Qian ; Wang, Zheng ; Taur, Yuan</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c263t-12bfa4cd5c70f6897046233bc16f3f55cacf858bf9ae74fb02be59bebae3fb733</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2017</creationdate><topic>Analytical models</topic><topic>Doping</topic><topic>Double gate (DG)</topic><topic>Electric potential</topic><topic>junctionless (JL)</topic><topic>Logic gates</topic><topic>MOSFET</topic><topic>MOSFETS</topic><topic>Semiconductor device modeling</topic><topic>short-channel effects (SCEs)</topic><topic>Silicon</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Xie, Qian</creatorcontrib><creatorcontrib>Wang, Zheng</creatorcontrib><creatorcontrib>Taur, Yuan</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE</collection><collection>CrossRef</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Xie, Qian</au><au>Wang, Zheng</au><au>Taur, Yuan</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Analysis of Short-Channel Effects in Junctionless DG MOSFETs</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>2017-08</date><risdate>2017</risdate><volume>64</volume><issue>8</issue><spage>3511</spage><epage>3514</epage><pages>3511-3514</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract>This brief investigates short-channel effects (SCEs) in junctionless (JL) double-gate (DG) MOSFETs analytically by solving the 2-D potential in subthreshold. Ids-Vg curves and Vt rolloff generated from the model are validated by 2-D numerical simulations (Technology Computer Aided Design). It is shown that the SCE of JL MOSFETs is inherently worse than that of undoped DG MOSFETs. The SCE worsens with increasing doping concentration in the channel.</abstract><pub>IEEE</pub><doi>10.1109/TED.2017.2716969</doi><tpages>4</tpages><orcidid>https://orcid.org/0000-0002-5232-0298</orcidid></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0018-9383 |
| ispartof | IEEE transactions on electron devices, 2017-08, Vol.64 (8), p.3511-3514 |
| issn | 0018-9383 1557-9646 |
| language | eng |
| recordid | cdi_ieee_primary_7987855 |
| source | IEEE |
| subjects | Analytical models Doping Double gate (DG) Electric potential junctionless (JL) Logic gates MOSFET MOSFETS Semiconductor device modeling short-channel effects (SCEs) Silicon |
| title | Analysis of Short-Channel Effects in Junctionless DG MOSFETs |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-04T19%3A01%3A25IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-crossref_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Analysis%20of%20Short-Channel%20Effects%20in%20Junctionless%20DG%20MOSFETs&rft.jtitle=IEEE%20transactions%20on%20electron%20devices&rft.au=Xie,%20Qian&rft.date=2017-08&rft.volume=64&rft.issue=8&rft.spage=3511&rft.epage=3514&rft.pages=3511-3514&rft.issn=0018-9383&rft.eissn=1557-9646&rft.coden=IETDAI&rft_id=info:doi/10.1109/TED.2017.2716969&rft_dat=%3Ccrossref_RIE%3E10_1109_TED_2017_2716969%3C/crossref_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=7987855&rfr_iscdi=true |