Embedded DRAM for a reconfigurable array

Embedded DRAM for a reconfigurable array

A field-programmable gate array, coupled with an on-chip 2 Mb DRAM bank has been designed, to aid in the study of the tradeoffs involved in the design of embedded DRAM for FPGAs. The memory can be used both as configuration storage, enabling reconfiguration in under 5 /spl mu/s, and application data...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Perissakis, S., Joo, Y., Ahn, J., Dellon, A., Wawraynek, J.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Bandwidth
Computer networks
Delay
Field programmable gate arrays
Logic arrays
Memory management
Microprocessors
Random access memory
Reconfigurable logic
Testing
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page 148
container_issue
container_start_page 145
container_title
container_volume
creator Perissakis, S.
Joo, Y.
Ahn, J.
Dellon, A.
Wawraynek, J.
description A field-programmable gate array, coupled with an on-chip 2 Mb DRAM bank has been designed, to aid in the study of the tradeoffs involved in the design of embedded DRAM for FPGAs. The memory can be used both as configuration storage, enabling reconfiguration in under 5 /spl mu/s, and application data memory, providing application logic executing on the array with up to 2 GB/sec data bandwidth. The variable latency of the DRAM is hidden from the logic by a stall mechanism and an SRAM-like interface.
doi_str_mv 10.1109/VLSIC.1999.797266
format Conference Proceeding
fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_797266</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>797266</ieee_id><sourcerecordid>797266</sourcerecordid><originalsourceid>FETCH-ieee_primary_7972663</originalsourceid><addsrcrecordid>eNpjYJA0NNAzNDSw1A_zCfZ01jO0tLTUM7c0NzIzY2bgMrE0NrAwNLY0NeNg4C0uzjIAAlMDc0MDY04GDdfcpNSUlNQUBZcgR1-FtPwihUSFotTk_Ly0zPTSosSknFSFxKKixEoeBta0xJziVF4ozc0g5eYa4uyhm5mamhpfUJSZm1hUGQ-x0xivJACeEi72</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Embedded DRAM for a reconfigurable array</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Perissakis, S. ; Joo, Y. ; Ahn, J. ; Dellon, A. ; Wawraynek, J.</creator><creatorcontrib>Perissakis, S. ; Joo, Y. ; Ahn, J. ; Dellon, A. ; Wawraynek, J.</creatorcontrib><description>A field-programmable gate array, coupled with an on-chip 2 Mb DRAM bank has been designed, to aid in the study of the tradeoffs involved in the design of embedded DRAM for FPGAs. The memory can be used both as configuration storage, enabling reconfiguration in under 5 /spl mu/s, and application data memory, providing application logic executing on the array with up to 2 GB/sec data bandwidth. The variable latency of the DRAM is hidden from the logic by a stall mechanism and an SRAM-like interface.</description><identifier>ISBN: 4930813956</identifier><identifier>ISBN: 9784930813954</identifier><identifier>DOI: 10.1109/VLSIC.1999.797266</identifier><language>eng</language><publisher>IEEE</publisher><subject>Bandwidth ; Computer networks ; Delay ; Field programmable gate arrays ; Logic arrays ; Memory management ; Microprocessors ; Random access memory ; Reconfigurable logic ; Testing</subject><ispartof>1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326), 1999, p.145-148</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/797266$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/797266$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Perissakis, S.</creatorcontrib><creatorcontrib>Joo, Y.</creatorcontrib><creatorcontrib>Ahn, J.</creatorcontrib><creatorcontrib>Dellon, A.</creatorcontrib><creatorcontrib>Wawraynek, J.</creatorcontrib><title>Embedded DRAM for a reconfigurable array</title><title>1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)</title><addtitle>VLSIC</addtitle><description>A field-programmable gate array, coupled with an on-chip 2 Mb DRAM bank has been designed, to aid in the study of the tradeoffs involved in the design of embedded DRAM for FPGAs. The memory can be used both as configuration storage, enabling reconfiguration in under 5 /spl mu/s, and application data memory, providing application logic executing on the array with up to 2 GB/sec data bandwidth. The variable latency of the DRAM is hidden from the logic by a stall mechanism and an SRAM-like interface.</description><subject>Bandwidth</subject><subject>Computer networks</subject><subject>Delay</subject><subject>Field programmable gate arrays</subject><subject>Logic arrays</subject><subject>Memory management</subject><subject>Microprocessors</subject><subject>Random access memory</subject><subject>Reconfigurable logic</subject><subject>Testing</subject><isbn>4930813956</isbn><isbn>9784930813954</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1999</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpjYJA0NNAzNDSw1A_zCfZ01jO0tLTUM7c0NzIzY2bgMrE0NrAwNLY0NeNg4C0uzjIAAlMDc0MDY04GDdfcpNSUlNQUBZcgR1-FtPwihUSFotTk_Ly0zPTSosSknFSFxKKixEoeBta0xJziVF4ozc0g5eYa4uyhm5mamhpfUJSZm1hUGQ-x0xivJACeEi72</recordid><startdate>1999</startdate><enddate>1999</enddate><creator>Perissakis, S.</creator><creator>Joo, Y.</creator><creator>Ahn, J.</creator><creator>Dellon, A.</creator><creator>Wawraynek, J.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>1999</creationdate><title>Embedded DRAM for a reconfigurable array</title><author>Perissakis, S. ; Joo, Y. ; Ahn, J. ; Dellon, A. ; Wawraynek, J.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_7972663</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1999</creationdate><topic>Bandwidth</topic><topic>Computer networks</topic><topic>Delay</topic><topic>Field programmable gate arrays</topic><topic>Logic arrays</topic><topic>Memory management</topic><topic>Microprocessors</topic><topic>Random access memory</topic><topic>Reconfigurable logic</topic><topic>Testing</topic><toplevel>online_resources</toplevel><creatorcontrib>Perissakis, S.</creatorcontrib><creatorcontrib>Joo, Y.</creatorcontrib><creatorcontrib>Ahn, J.</creatorcontrib><creatorcontrib>Dellon, A.</creatorcontrib><creatorcontrib>Wawraynek, J.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Perissakis, S.</au><au>Joo, Y.</au><au>Ahn, J.</au><au>Dellon, A.</au><au>Wawraynek, J.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Embedded DRAM for a reconfigurable array</atitle><btitle>1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)</btitle><stitle>VLSIC</stitle><date>1999</date><risdate>1999</risdate><spage>145</spage><epage>148</epage><pages>145-148</pages><isbn>4930813956</isbn><isbn>9784930813954</isbn><abstract>A field-programmable gate array, coupled with an on-chip 2 Mb DRAM bank has been designed, to aid in the study of the tradeoffs involved in the design of embedded DRAM for FPGAs. The memory can be used both as configuration storage, enabling reconfiguration in under 5 /spl mu/s, and application data memory, providing application logic executing on the array with up to 2 GB/sec data bandwidth. The variable latency of the DRAM is hidden from the logic by a stall mechanism and an SRAM-like interface.</abstract><pub>IEEE</pub><doi>10.1109/VLSIC.1999.797266</doi></addata></record>
fulltext fulltext_linktorsrc
identifier ISBN: 4930813956
ispartof 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326), 1999, p.145-148
issn
language eng
recordid cdi_ieee_primary_797266
source IEEE Electronic Library (IEL) Conference Proceedings
subjects Bandwidth
Computer networks
Delay
Field programmable gate arrays
Logic arrays
Memory management
Microprocessors
Random access memory
Reconfigurable logic
Testing
title Embedded DRAM for a reconfigurable array
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-26T20%3A45%3A53IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Embedded%20DRAM%20for%20a%20reconfigurable%20array&rft.btitle=1999%20Symposium%20on%20VLSI%20Circuits.%20Digest%20of%20Papers%20(IEEE%20Cat.%20No.99CH36326)&rft.au=Perissakis,%20S.&rft.date=1999&rft.spage=145&rft.epage=148&rft.pages=145-148&rft.isbn=4930813956&rft.isbn_list=9784930813954&rft_id=info:doi/10.1109/VLSIC.1999.797266&rft_dat=%3Cieee_6IE%3E797266%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=797266&rfr_iscdi=true