Embedded DRAM for a reconfigurable array

Embedded DRAM for a reconfigurable array

A field-programmable gate array, coupled with an on-chip 2 Mb DRAM bank has been designed, to aid in the study of the tradeoffs involved in the design of embedded DRAM for FPGAs. The memory can be used both as configuration storage, enabling reconfiguration in under 5 /spl mu/s, and application data...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Perissakis, S., Joo, Y., Ahn, J., Dellon, A., Wawraynek, J.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Bandwidth
Computer networks
Delay
Field programmable gate arrays
Logic arrays
Memory management
Microprocessors
Random access memory
Reconfigurable logic
Testing
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Beschreibung
Zusammenfassung:A field-programmable gate array, coupled with an on-chip 2 Mb DRAM bank has been designed, to aid in the study of the tradeoffs involved in the design of embedded DRAM for FPGAs. The memory can be used both as configuration storage, enabling reconfiguration in under 5 /spl mu/s, and application data memory, providing application logic executing on the array with up to 2 GB/sec data bandwidth. The variable latency of the DRAM is hidden from the logic by a stall mechanism and an SRAM-like interface.
DOI:10.1109/VLSIC.1999.797266