A 12.4 mW CMOS front-end for a 5 GHz wireless-LAN receiver

A 12.4 mW CMOS front-end for a 5 GHz wireless-LAN receiver

This paper presents a 12.4 mW front-end for a 5 GHz wireless-LAN receiver fabricated in a 0.24 /spl mu/m CMOS technology. It consists of an LNA, mixers and an automatically tuned third-order filter controlled by a low-power PLL. The filter attenuates the image-signal by an additional 12 dB beyond wh...

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Bibliographische Detailangaben
Hauptverfasser: Samavati, H., Rategh, H.R., Lee, T.H.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
CMOS technology
FCC
Filters
Noise figure
Phase locked loops
Radio frequency
Radio spectrum management
Signal to noise ratio
Voltage-controlled oscillators
Wireless LAN
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Beschreibung
Zusammenfassung:This paper presents a 12.4 mW front-end for a 5 GHz wireless-LAN receiver fabricated in a 0.24 /spl mu/m CMOS technology. It consists of an LNA, mixers and an automatically tuned third-order filter controlled by a low-power PLL. The filter attenuates the image-signal by an additional 12 dB beyond what can be achieved by an image-reject architecture. The filter also reduces the noise contribution of the cascode devices in the LNA core. The LNA/filter combination has a noise figure of 4.8 dB and the overall noise figure of the signal path is 5.2 dB. The overall IIP3 is -2 dBm.
DOI:10.1109/VLSIC.1999.797245