A Low-Power Analog Delay Line Using a Current-Splitting Method for 3-D Ultrasound Imaging Systems

We propose an analog delay line (ADL) that adopts a current-splitting method (CSM) to reduce power consumption. The proposed ADL employs a pipelined sample-and-hold architecture and includes a buffer in the analog memory cell to prevent a charge sharing problem. The CSM reduces power consumption without distorting the sampled data by dividing the current source of the buffer into a holding current source and a buffering current source, which are, respectively, located inside and outside of the analog memory cell. The simulated power consumption of the proposed ADL without and with the CSM is 1080 and 90~{\mu }\text{W} , respectively, indicating that the CSM reduces power consumption by 91.7%. The proposed ADL was fabricated using a 0.18- {\mu }\text{m} CMOS process with a 1.8-V supply voltage and occupies an active area of 120 \times 140~{ \mu }\text{m}^{ 2} . The sampling capacitor in the analog memory cell was implemented with MOS capacitors instead of metal-insulator-metal capacitors, resulting in an area per unit delay of the proposed ADL of only 600~{ \mu }\text{m}^{ 2} , which is much smaller than that in prior works. The measurement results show that the delay of the proposed ADL is accurately controlled from 25 to 475 ns with a unit delay step of 25 ns at a sampling frequency of 40 MHz.