DRAF: A Low-Power DRAM-based Reconfigurable Acceleration Fabric

FPGAs are a popular target for application-specific accelerators because they lead to a good balance between flexibility and energy efficiency. However, FPGA lookup tables introduce significant area and power overheads, making it difficult to use FPGA devices in environments with tight cost and power constraints. This is the case for datacenter servers, where a modestly-sized FPGA cannot accommodate the large number of diverse accelerators that datacenter applications need.This paper introduces DRAF, an architecture for bit-level reconfigurable logic that uses DRAM subarrays to implement dense lookup tables. DRAF overlaps DRAM operations with routing latency to minimize the impact of DRAM latency. It also supports multiple configuration contexts that can be used to quickly switch between different accelerators. Overall, DRAF trades off some performance of FPGAs for significant gains in area and power. DRAF improves area density by 10x over FPGAs and power consumption by 3x, enabling DRAF to satisfy demanding applications within strict power and cost constraints. While accelerators mapped to DRAF are 2-3x slower than those in FPGAs, they still deliver a 13x speedup and an 11x reduction in power consumption over a Xeon core for a wide range of datacenter tasks.