Parallelization of algorithms for a system of digital signal processors

In this paper, the implementation of computationally intensive algorithms on a parallel system of digital signal processors (DSPs) is examined. The used parallelization technique is based on methods of the design of parallel processor arrays. The parameters of the DSP system, such as computation and communication time, size and access time of the memory, are included into the parallelization methods. The efficiency of the parallel solutions is demonstrated by means of implementations of algorithms for solving systems of linear equations.