Implementation of 2^\,- \,2^\,- \,1 Modulo Adder Based RFID Mutual Authentication Protocol

In wireless communication, secure transmission and reception of data are the major concern today. In recent years, Radio Frequency Identification (RFID) has played a vital role in the security system for secured data communication. The main challenge in RFID-based security system is to design a more secure, better area and power efficient encoder architecture for tag-reader mutual authentication protocol. This paper proposes new and efficient encoder architecture for RFID mutual authentication protocol which utilizes 2 n - 2 k - 1 modulo adder for achieving higher security. The proposed architecture is described in Verilog hardware description language and the functionalities are verified and synthesized using Altera Quartus II tool. The architecture is also synthesized using Cadence RTL compiler for 180 and 90 nm technology. Experimental results of the proposed scheme give better performances in terms of area, power, and delay when compared with existing mutual authentication schemes. In addition to that, the architecture is realized as hardware in Altera DE2 Cyclone II (EP2C35F672C6) field programmable gate array and real time verification has been carried out using Logic Analyzer 16851A. Finally, formal security analysis has been performed using the Burrows-Abadi-Needham (BAN) logic to show that the proposed protocol is secure.