1200 V SiC IE-UMOSFET with low on-resistance and high threshold voltage

A critical issue with the SiC UMOSFET is the need to develop a shielding structure for the gate oxide at the trench bottom without any increase in the JFET resistance. This study describes our new UMOSFET named IE-UMOSFET, which we developed to cope with this trade-off. A simulation showed that a low on-resistance is accompanied by an extremely low gate oxide field even with a negative gate voltage. The low R onA was sustained as V th increases. The R onA values at V G =25 V (E ox =3.2 MV/cm) and V G =20V (E ox =2.5 MV/cm), respectively, for the 3mm × 3mm device were 2.4 and 2.8 mΩcm 2 with a lowest V th of 2.4 V, and 3.1 and 4.4 mΩcm 2 with a high V th of 5.9 V.