A new DC voltage-voltage method to measure the interface traps in deep sub-micron MOS transistors

A direct-current voltage-voltage (DCVV) technique for the measurement of stress-generated interface traps in sub-micron metal-oxide-semiconductor transistors (MOSTs) is demonstrated. This method uses the source-bulk-drain structure of a sub-micron MOST as an effective lateral bipolar transistor when the channel region is out of inversion under the control of the gate voltage V/sub gb/. The emitter injects the minority carriers into the base region and the collector is open. The V/sub cb/ versus V/sub gb/ spectrum can be explained quantitatively using the extended Ebers-Moll equations and interface trap Shockley-Read-Hall (SRH) recombination. A single effective interface trap at the source or drain side could be detected, and interface traps at the source side can be separated from those at the drain side by the new method.