Copper-SilK integration in a 0.18 /spl mu/m double level metal interconnect

Copper-SilK integration in a 0.18 /spl mu/m double level metal interconnect

This paper describes the integration of copper and SilK in a 0.18 /spl mu/m DLM interconnect. The main integration issues such as dual damascene patterning, SilK porosity and copper filling have been addressed, as shown by the 0.5 /spl Omega/-100% yield obtained for 0.3 /spl mu/m vias. The Cu/SilK i...

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Hauptverfasser: Demolliens, O., Berruyer, P., Morand, Y., Tabone, C., Roman, A., Cochet, M., Assous, M., Feldis, H., Blanc, R., Tabouret, E., Louis, D., Arvet, C., Lajoinie, E., Gobil, Y., Passemard, G., Jourdan, F., Moussavi, M., Cordeau, M., Morel, T., Mourier, T., Ulmer, L., Sicurani, E., Tardif, F., Beverina, A., Trouillet, Y., Renaud, D.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Cleaning
Copper
Degradation
Electrical resistance measurement
Etching
Filling
Lithography
Metallization
Temperature measurement
Tin
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Beschreibung
Zusammenfassung:This paper describes the integration of copper and SilK in a 0.18 /spl mu/m DLM interconnect. The main integration issues such as dual damascene patterning, SilK porosity and copper filling have been addressed, as shown by the 0.5 /spl Omega/-100% yield obtained for 0.3 /spl mu/m vias. The Cu/SilK interest is confirmed by a 40% RC reduction compared to a Cu-SiO/sub 2/ structure.
DOI:10.1109/IITC.1999.787121