A Novel SuperSteep Subthreshold Slope Dual-Channel FET Utilizing a Gate-Controlled Thyristor Mode-Induced Positive Feedback Current

For the first time, we experimentally demonstrate an FET with a polycrystalline silicon (poly-Si) device featuring supersteep subthreshold slope (SS) around 20 mV/decade at room temperature. This novel dual-channel device is a three-wordline(WL) transistor fabricated in a poly-Si channel, with p + source and n + drain. The outer two WLs serve as the pass gates that control the virtual junction of the center WL device (main gate). Whether n-channel or p-channel characteristics are achieved depend on the bias polarity applied to the pass gates. Both read modes exhibit supersteep SS behavior for the center main gate. Theoretical analysis suggests that this three-WL FET device creates a gate-controlled thyristor mode, where a positive feedback current is induced when the center main gate voltage is above the onset value to induce the turnedon thyristor. Different from the usual tunneling FET (with reverse-biased junction bias), the p + /n + junction is forward biased, and thus, the read current can approach 10 μA even for a narrow-width (~32 nm) poly-Si thin-film transistor, amounting to 0.3-mA/μm drive current. This device displays no hysteresis between forward and reverse voltage sweeping, and the steep SS has weak temperature/size dependence.