Differential 0.35 /spl mu/m CMOS circuits for 622 MHz/933 MHz monolithic clock and data recovery applications

Fully-differential CMOS circuits are presented for high speed Clock and Data Recovery (CDR) applications. The design is part of an integrated physical layer controller for an OC-12 ATM system, but can be used in other systems operating in 622 MHz-933 MHz range. Building blocks are presented including novel designs for VCO and charge pump. Two chips are implemented in 0.35 /spl mu/m CMOS. One contains partitioned building blocks of a PLL-based CDR that, together with an external loop filter, can be used for flexible testing and application at a desired frequency. The other chip is a monolithic CDR with integrated loop filter particularly designed for application on 622 Mb/s NRZ data.