A 65-nm CMOS Constant Current Source With Reduced PVT Variation
This paper presents a new nanometer-based low-power constant current reference that attains a small value in the total process-voltage-temperature variation. The circuit architecture is based on the embodiment of a process-tolerant bias current circuit and a scaled process-tracking bias voltage sour...
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| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2017-04, Vol.25 (4), p.1373-1385 |
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| container_title | IEEE transactions on very large scale integration (VLSI) systems |
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| creator | Wang, Dong Tan, Xiao Liang Chan, Pak Kwong |
| description | This paper presents a new nanometer-based low-power constant current reference that attains a small value in the total process-voltage-temperature variation. The circuit architecture is based on the embodiment of a process-tolerant bias current circuit and a scaled process-tracking bias voltage source for the dedicated temperature-compensated voltage-to-current conversion in a preregulator loop. Fabricated in a UMC 65-nm CMOS process, it consumes 7.18 μW with a 1.4 V supply. The measured results indicate that the current reference achieves an average temperature coefficient of 119 ppm/°C over 12 samples in a temperature range from -30 °C to 90 °C without any calibration. Besides, a low line sensitivity of 180 ppm/V is obtained. This paper offers a better sensitivity figure of merit with respect to the reported representative counterparts. |
| doi_str_mv | 10.1109/TVLSI.2016.2633566 |
| format | Article |
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The circuit architecture is based on the embodiment of a process-tolerant bias current circuit and a scaled process-tracking bias voltage source for the dedicated temperature-compensated voltage-to-current conversion in a preregulator loop. Fabricated in a UMC 65-nm CMOS process, it consumes 7.18 μW with a 1.4 V supply. The measured results indicate that the current reference achieves an average temperature coefficient of 119 ppm/°C over 12 samples in a temperature range from -30 °C to 90 °C without any calibration. Besides, a low line sensitivity of 180 ppm/V is obtained. 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| subjects | Current reference line sensitivity process tracking Resistors Sensitivity temperature compensation Temperature distribution Temperature sensors threshold voltage (<italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">V ) circuit Topology Transistors |
| title | A 65-nm CMOS Constant Current Source With Reduced PVT Variation |
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