CMOS distributed amplifier design using CAD optimization techniques

CMOS distributed amplifier design using CAD optimization techniques

A four-stage distributed amplifier exhibits 6.5 dB gain, 5.5 GHz bandwidth, and 80 mW power dissipation from a 3 V supply in 0.6 /spl mu/m CMOS. Scalable inductor models and custom CAD tools optimize performance.

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Allstot, D.J., Ballweber, B.M., Gupta, R.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Bandwidth
Design automation
Design optimization
Distributed amplifiers
Geometry
Inductance
Inductors
Packaging
Radiofrequency integrated circuits
Semiconductor device modeling
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A four-stage distributed amplifier exhibits 6.5 dB gain, 5.5 GHz bandwidth, and 80 mW power dissipation from a 3 V supply in 0.6 /spl mu/m CMOS. Scalable inductor models and custom CAD tools optimize performance.
DOI:10.1109/SSMSD.1999.768607