Parametric built-in self-test of VLSI systems

Conventionally, Automatic Test Equipment (ATE) has been used for parametric tests of VLSI systems to determine the influence of clock speed, supply voltage, and temperature on the specified functionality of the circuit under test. This method is likely to become infeasible in the near future due to an aggressive drive to increased Overall Timing Accuracy (OTA), as predicted in the SIA Roadmap. In this paper, a method for Parametric Built-in Self-Test using on-chip Phase-Locked Loops (PLLs) is presented which is capable of overcoming the timing accuracy problem. A PLL-based test circuitry to determine the maximum frequency is described. Design constraints of the PLL control system, such as stability and resolution, are discussed for a specific design using 0.35 /spl mu/m CMOS technology. The functionality of the self-test circuitry is demonstrated to be competitive with parametric ATE tests such as Global Search Track without the need for expensive test equipment.