A 12 ns 8 MB DRAM secondary cache for a 64 b microprocessor

The most important advantage of on-chip DRAMs is high bandwidth between a DRAM and a processor. Many circuit technologies are used to enlarge the bandwidth. For example, sense amplifier data are extracted by a number of data-lines parallel to the bit-lines in some DRAMs. Even if these circuits are used, random accesses substantially degrade the bandwidth because row-address access and cycle time (tRAC) are much larger than column-address access and burst cycle time in conventionally designed DRAMs. Small tRAC is not essential in conventional graphic applications because of periodicity and locality of their memory accesses. However, the large tRAC has prevented DRAMs from being widely used as on-chip secondary caches. To achieve 12ns row-address access, a 5.75Mb cell array of the DRAM core is divided into 16kb subarrays by sense amplifiers (SAs) and sub-word drivers (SWDs).