Impact Ionization in SOI MESFETs at the 32-nm Node

Silicon metal-semiconductor FETs (MESFETs) have been fabricated using a 32-nm silicon-on-insulator (SOI) CMOS technology. The MESFET gates are formed during the self-aligned silicide step and show almost ideal Schottky behavior at low drain voltages. However, an anomalous peak in the reverse gate le...

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Veröffentlicht in:IEEE transactions on electron devices 2016-10, Vol.63 (10), p.4143-4146
Hauptverfasser: Thornton, Trevor J., Lepkowski, William, Wilk, Seth J.
Format: Artikel
Sprache:eng
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Zusammenfassung:Silicon metal-semiconductor FETs (MESFETs) have been fabricated using a 32-nm silicon-on-insulator (SOI) CMOS technology. The MESFET gates are formed during the self-aligned silicide step and show almost ideal Schottky behavior at low drain voltages. However, an anomalous peak in the reverse gate leakage current appears for drain voltages ≥2 V. The anomalous gate current is attributed to impact ionization generating excess holes that exit the channel through the Schottky contact. An analytical model is used to extract the electron impact ionization rate, α, which agrees with three earlier data sets over nearly four orders of magnitude.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2016.2601241