A New Compiler-Directed Cache Coherence Scheme for Shared Memory Multiprocessors with Fast and Parallel Explicit Invalidation

We propose a novel compiler-directed cache management scheme which allows parallel invalidation of a subset of array elements. The scheme limits non-stale data invalidations using a novel memory allocation technique. Its correctness is proved using a flow graph model. It is also shown that the schem...

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Bibliographische Detailangaben

Hauptverfasser:	Louri, A., Hongki Sung
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Application software Coherence Computer science Delay Engineering management Flow graphs Registers Runtime
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